1. Field of The Invention
The present invention relates generally to a variable delay circuit.
2. Description of The Related Art
Referring to FIGS. 3 through 8, some examples of conventional variable delay circuits will be described below.
The construction of a first conventional variable delay circuit 20 is shown in FIG. 3. This variable delay circuit is called a current stubbed inverter comprising P-channel MOS transistors 22, 23 and N-channel MOS transistors 24, 25, and widely used for PLL circuits, DLL circuits and so forth. The variable delay circuit 20 is designed so that a charging current of a load capacity supplied from a power supply 28 by controlling voltages V.sub.cp, V.sub.cn, which are applied to the gates of the transistors 22, 25 when a trailing edge signal is inputted to an input terminal 21, is changed by ON resisters R of the transistors 22, 25 and a parasitic capacity C to optionally set a delay time of a leading edge signal appearing at an output terminal 27. Furthermore, the voltage V.sub.cn is an inverted signal of the voltage V.sub.cp.
In the first conventional example, it is required to very precisely control the voltages V.sub.cp, V.sub.cn in order to obtain a high resolution, so that it is difficult to use the variable delay circuit for a CMOS semiconductor integrated circuit having a large variation in process.
The construction of a second conventional variable delay circuit 30 is shown in FIG. 4. This variable delay circuit 30 comprises an inverter 31 comprising a P-channel MOS transistor 32 and an N-channel MOS transistor 34, and a transfer gate 36 connected to an output terminal of the inverter 31 in series. The gate voltages V.sub.cp, V.sub.cn of the transfer gate 36 are controlled to make a series resister (on resister) variable, so that an RC time constant varies to allow a propagation delay time to vary.
In the second conventional example similar to the first conventional example, there is a problem in that it is required to very precisely control the voltages V.sub.cp, V.sub.cn so that it is not possible to use the variable delay circuit for a CMOS semiconductor integrated circuit having a large variation in process.
The construction of a third conventional variable delay circuit 40 is shown in FIG. 5. This variable delay circuit 40 comprises an inverter comprising a P-channel MOS transistor 42 and an N-channel MOS transistor 44, and a variable load capacitor 46 connected to an output terminal 47 of the inverter. The load capacitor 46 is adjusted to change an RC time constant to allow a propagation delay time to vary. In the third conventional example, it is typically realized by controlling using, e.g., an analog switch, whether the load capacitor 46 having a predetermined capacity is connected to the output terminal 47. Therefore, there is a problem in that it is difficult to precisely control a propagation delay time under the influence of a parasitic capacity added by connecting control means, such as the analog switch, to the output terminal 47.
In addition, the precision of the production of the capacitor must be high, so that it is very difficult to produce variable delay circuits in large quantities in view of the variation in CMOS producing process.
The construction of a fourth conventional variable delay circuit 50 is shown in FIG. 6. This variable delay circuit 50 has an inverter comprising a P-channel MOS transistor 52 and an N-channel MOS transistor 54. By controlling the back gate voltage of each of these transistors 52, 54, the threshold voltage of each of the transistors 52, 54 is controlled to adjust a propagation delay time. In the fourth delay circuit, it is required to enhance the control precise of the back gate voltage in order to obtain a high resolution, so that it is difficult to realize the delay circuit for a CMOS semiconductor integrated circuit having a great variation in producing process.
The construction of a fifth conventional variable delay circuit is shown in FIG. 7. This delay circuit has a plurality of delay parts 5.sub.1, . . . , 5.sub.n which are cascade-connected. Each of the delay parts 5.sub.i (i=1, . . . , n) comprises a delay element 3.sub.i, a multiplexer 2.sub.i for selecting whether an input signal is allowed to pass through the delay element 3.sub.i and an OR gate 4.sub.i for transmitting an output of the selected delay element or the input signal to the subsequent stage of delay part.
Even if the fifth conventional variable delay circuit is used, it is not ensured to obtain a desired delay time. The delay time of the variable delay circuit is determined by the set value Span of the maximum delay time and a resolution (the minimum delay time) Res. An optional delay time thus obtained is about integer times as large as the resolution Res.
A conventional example of a variable delay circuit capable of solving the problem of the fifth conventional variable delay circuit will be described as a sixth conventional variable delay circuit.
The construction of the sixth conventional variable delay circuit will be described in FIG. 8. This delay circuit is disclosed in Japanese Patent Laid-Open No. 2582250. This delay circuit is formed by providing the variable delay circuit of FIG. 7 with a control circuit 6 for controlling each stage of multiplexer. In order to obtain a desired delay time, the set delay time value D.sub.k of each delay element 3.sub.k (k=1, . . . , n) is defined so as to satisfy the following formulae. ##EQU1##
wherein when EQU k=1, D.sub.1 ={Res/(1+da)}/(1+dr) (1b)
wherein Res is a resolution of a variable delay circuit, da being an absolute value of an absolute error at a designed delay time D.sub.k, and dr being an absolute value of a relative error.
The actual delay time value of each delay element 3.sub.k is equal to the designed value if there is no error, and the characteristic thereof is shown by line g.sub.0 in FIG. 9. However, this characteristic varies due to the variation in producing process, the fluctuation of working environment (temperature and power supply voltage) and so forth, so that the characteristic is included in a region between lines g.sub.1 and g.sub.2 in FIG. 9. This region of the variation in characteristic corresponds to the absolute error da (see FIG. 9). Even in the case of substantially the same characteristic, there is a variation of the characteristic as shown by points P.sub.1, P.sub.2 in FIG. 9. This variation corresponds to the relative error dr.
In the sixth conventional variable delay circuit, as can be seen from formulae (1a) and (1b), the set delay time value D.sub.k of each delay elements 3.sub.k (k=1, . . , n) is derived on the basis of the preset resolution Res, the absolute error da and the relative error dr. In this case, the designed delay time values are sequentially derived in order of smaller value.
Thus, each delay element 3.sub.k (k=1, . . . , n) is derived. When the maximum delay time derived from the delay times D.sub.1, . . . , D.sub.n of the delay elements 3.sub.1, . . . , 3.sub.n is smaller than the predetermined value Span previously given, a delay element 3.sub.n+1 is newly added so that the resulting maximum delay time is greater than the predetermined value Span. At this time, the delay time of the added delay element 3.sub.n+1 is set so as to satisfy formula (1a). Therefore, the delay time D.sub.n+1 of the added delay element has a greater value than any delay time values D.sub.i (i=1, . . . , n) of other delay elements 3.sub.1, . . . , 3.sub.n. For that reason, there is a problem in that the circuit scale of a variable delay circuit increases.